100 ÷ 16 = 6 remainder 4. So decimal 100 equals 64₁₆. In binary it is 0110 0100, matching hex digits 6 and 4.
Hexadecimal 7B equals decimal
A 123
B 111
C 135
D 145
7B₁₆ = 7×16 + 11. Since B is 11, total is 112 + 11 = 123. Hex is a compact form for binary values.
Binary 101101₂ equals octal
A 65₈
B 75₈
C 55₈
D 45₈
Group into 3 bits: 101 101. Each 101₂ is 5, so the octal number is 55₈. Grouping by 3 makes binary↔octal conversion fast.
Octal 70₈ equals decimal
A 54
B 58
C 60
D 56
70₈ = 7×8 + 0 = 56. Octal is base-8, so each left shift multiplies by 8, similar to powers of 10 in decimal.
Binary addition: 1111 + 0001 equals
A 1110
B 10000
C 1000
D 0111
1111₂ is 15. Adding 1 gives 16, which is 10000₂. This shows carry propagation across multiple bits in binary addition.
In unsigned 8-bit, 255 + 1 becomes
A 0
B 255
C 256
D 1
8-bit unsigned cannot store 256. 255 is 11111111₂; adding 1 produces 1 00000000₂. The extra carry is discarded, leaving 00000000₂ (0).
In 8-bit 2’s complement, 127 + 1 gives
A 128
B 0
C −128
D −127
127 is 01111111₂. Adding 1 gives 10000000₂, which represents −128 in 2’s complement. This is a signed overflow because true result +128 is out of range.
1’s complement subtraction uses
A Add with carry end
B Add without carry
C Multiply then add
D Divide then subtract
In 1’s complement subtraction, you add the 1’s complement of the subtrahend. If an end-around carry occurs, it is added back to the result to get the correct answer.
In 2’s complement subtraction, end-around carry is
A Always added back
B Converted to borrow
C Stored as sign
D Always ignored
In 2’s complement arithmetic, subtraction is done by adding the 2’s complement. Any carry out of the MSB is discarded; no end-around carry is added back.
In 2’s complement, to represent −5 in 8 bits, start from
A 11111010
B 11111011
C 00000101
D 10000101
To form −5, first write +5 as 00000101₂. Then invert bits to 11111010 and add 1 to get 11111011, which is −5 in 8-bit 2’s complement.
8-bit 2’s complement for −5 is
A 11111011
B 11111010
C 10000101
D 00000101
+5 is 00000101₂. Invert gives 11111010, add 1 gives 11111011. That final pattern is the standard 2’s complement representation for −5.
In signed 2’s complement, adding two negatives yields positive when
A Carry occurs
B Overflow happens
C No carry occurs
D Inputs differ
If two negative numbers produce a positive result, the true sum exceeded the negative range and wrapped around. That sign flip is a classic indicator of signed overflow.
A Boolean expression output is always
A 0–9 digits
B A–F letters
C 0,1 only
D Any real value
Boolean algebra deals with two logic states: 0 (false) and 1 (true). All Boolean operations and logic circuit outputs are interpreted using these two values only.
In Boolean algebra, the OR operator is often written as
A +
B ·
C ⊕
D ¬
In Boolean notation, OR is commonly shown by “+”, AND by “·”, NOT by a bar or prime, and XOR by ⊕. This is different from arithmetic meanings.
In Boolean algebra, the AND operator is often written as
A +
B ⊕
C =
D ·
AND is often written as a dot or by simple adjacency (AB). It means both conditions must be true for the output to be 1.
The complement of A is written as
A A+1
B A·1
C A’
D A²
Complement means logical NOT. A’ (or Ā) equals 1 when A is 0, and equals 0 when A is 1. It is used to express inverse conditions.
Double negation rule means
A (A’)’ = A
B A’ = A
C A + A = 0
D A·A’ = 1
Applying NOT twice returns the original value. This is a basic Boolean rule and helps simplify expressions containing multiple complements.
Simplify: A·0 + B equals
A 0
B A
C A+B
D B
A·0 is always 0, so expression becomes 0 + B, which equals B. This uses null law for AND and identity law for OR.
Simplify: (A + 0)·B equals
A A
B B
C A·B
D A+B
A + 0 simplifies to A by identity law of OR. Then expression becomes A·B. Such stepwise simplification reduces gate count in circuits.
De Morgan form of (A + B)’ is
A A’·B’
B A’ + B’
C A·B
D (A·B)’
De Morgan’s law states (A + B)’ equals A’·B’. This is used when converting between OR-then-NOT and AND of inverted inputs in gate designs.
De Morgan form of (A·B)’ is
A A’·B’
B A’ + B’
C A + B
D (A+B)’
Another De Morgan law is (A·B)’ = A’ + B’. It helps replace NAND-style expressions with OR of inverted inputs, useful for simplification.
Which gate set can implement any Boolean function alone
A NAND only
B AND only
C OR only
D XOR only
NAND is universal. Using only NAND gates, you can build NOT, AND, OR, and then any complex logic. This makes hardware implementations economical and consistent.
A 2-to-1 multiplexer has select lines
A 0
B 2
C 1
D 3
A 2-to-1 MUX selects between two inputs using one select bit. When select is 0 it chooses input0; when select is 1 it chooses input1.
A 4-to-1 multiplexer needs select lines
A 1
B 3
C 4
D 2
A 4-to-1 MUX must select one of four inputs. Two select bits provide 2² = 4 combinations, enough to choose any one input.
A 1-to-4 demultiplexer needs select lines
A 1
B 2
C 3
D 4
A 1-to-4 DEMUX routes one input to one of four outputs. Two select lines give four possible output choices, matching the required destinations.
A half adder “Sum” output equals
A XOR
B AND
C OR
D XNOR
Half adder sum is XOR because it is 1 when inputs differ (01 or 10). The carry output is AND because carry happens only when both inputs are 1.
A half adder “Carry” output equals
A XOR
B OR
C AND
D NOT
Carry is produced only when both bits are 1, which matches the AND truth table. This is why half adders are commonly built with XOR for sum and AND for carry.
A full adder “Sum” equals
A A⊕B⊕Cin
B A+B+Cin
C A·B·Cin
D (A·B)’
Full adder sum is XOR of all three inputs. It becomes 1 when an odd number of inputs are 1, matching binary addition behavior for a single-bit sum.
A full adder “Carry out” is 1 when
A All inputs 0
B Exactly one 1
C Inputs all different
D At least two 1s
Carry out occurs if two or more of A, B, Cin are 1. That condition can be expressed as AB + ACin + BCin, which matches full adder carry logic.
A flip-flop is mainly a
A Combinational circuit
B Power supply
C Memory element
D Display device
Flip-flops store one bit of information and change state based on clock/control signals. They are basic building blocks of registers, counters, and sequential logic circuits.
Combinational logic output depends on
A Present inputs only
B Past state only
C Clock frequency only
D Power rating only
Combinational circuits have no memory. Their outputs at any moment are determined only by the current input values, unlike sequential circuits that also depend on stored state.
Sequential logic output depends on
A Present inputs only
B Past state also
C Wire length only
D Screen pixels only
Sequential circuits include memory elements like flip-flops. Therefore outputs depend on current inputs and the previous stored state, making them suitable for counters and control logic.
BCD for decimal digit 9 is
A 1010
B 1111
C 1001
D 0111
In BCD, each decimal digit 0–9 is encoded using 4 bits. Decimal 9 corresponds to binary 1001. Values 1010 to 1111 are invalid BCD digits.
Which 4-bit codes are invalid in BCD
A 1010–1111
B 0000–1001
C 0001–1110
D 0010–1100
BCD encodes only digits 0–9, which are 0000 to 1001. The remaining six patterns 1010 to 1111 do not represent any decimal digit in standard BCD.
Gray code adjacent values differ by
A Two bits
B Three bits
C Four bits
D One bit
Gray code is designed so consecutive numbers differ by only one bit. This reduces errors in mechanical or noisy sensing systems because only one bit changes at a time.
An ASCII code typically represents
A Logic gate output
B CPU instruction
C Character symbol
D Memory address
ASCII assigns numeric codes to characters like letters, digits, and symbols. Computers store and transmit text by using these numeric values instead of the visible characters.
In basic ASCII, total characters are
A 64
B 128
C 96
D 256
Basic ASCII uses 7 bits, allowing 2⁷ = 128 codes. These include control codes, uppercase/lowercase letters, digits, and common punctuation marks.
A parity bit checks for
A Single-bit errors
B Faster processing
C Data compression
D Multi-bit storage
Parity is a simple error-detection method. If one bit flips during transmission, the parity check fails. It cannot reliably correct errors and may miss some even-numbered bit errors.
Odd parity means total 1s are
A Always even
B Always zero
C Always prime
D Always odd
Odd parity adds a parity bit so the total count of 1 bits becomes odd. Receiver recomputes the count; mismatch indicates a likely transmission or storage error.
A decoder output is typically
A One active line
B Multiple active lines
C Random pattern
D Floating value
For a valid input code, a decoder usually activates exactly one output line (one-hot output). This is useful for selecting memory locations or enabling one device among many.
A priority encoder resolves
A No active inputs
B Decimal arithmetic
C Multiple active inputs
D Floating errors
If more than one input is active, a priority encoder outputs the code of the highest-priority active input. This avoids ambiguity and is used in interrupt handling and arbitration.
A K-map group size must be
A Power of two
B Any number
C Prime number
D Always three
K-map grouping uses rectangles of 1, 2, 4, 8, etc. cells. Power-of-two grouping ensures valid simplification by eliminating variables systematically.
In a K-map, adjacency includes
A Diagonal cells only
B Center cell only
C Random neighbors
D Wrap-around edges
K-maps treat opposite edges as adjacent (wrap-around). This reflects Gray code ordering and allows larger groups, leading to more simplification than a simple grid adjacency.
XOR can be used to generate
A Clock pulses
B Power supply
C Parity bit
D Screen pixels
XOR outputs 1 when an odd number of inputs are 1. By XOR-ing data bits, you can produce an even/odd parity bit for simple error detection in communication.
XNOR is commonly used for
A Data storage
B Equality checking
C Voltage regulation
D File compression
XNOR outputs 1 when inputs are equal. With multiple bits, XNOR results can be combined to test whether two binary numbers match, forming the base of digital comparators.