Chapter 5: Number System and Digital Logic (Set-5)
A 9-bit unsigned register can represent values up to
A 255
B 512
C 1023
D 511
Explanation: Unsigned n-bit maximum is 2ⁿ−1. For 9 bits, 2⁹−1 = 512−1 = 511. The maximum pattern is 111111111₂.
For 9-bit 2’s complement, the positive maximum is
A 256
B 257
C 255
D 511
Explanation: In n-bit 2’s complement, max positive is 2^(n−1)−1. For 9 bits, that is 2⁸−1 = 255. Range becomes −256 to +255.
For 9-bit 2’s complement, the most negative value is
A −255
B −256
C −257
D −511
Explanation: In n-bit 2’s complement, minimum is −2^(n−1). With 9 bits, minimum is −2⁸ = −256, represented by 100000000₂.
In 2’s complement, the binary 01111111 (8-bit) equals
A −127
B 128
C −128
D 127
Explanation: MSB is 0, so it’s positive. The value is 127 because all lower 7 bits are 1: 64+32+16+8+4+2+1 = 127.
In 8-bit 2’s complement, 10000001 represents
A −128
B −1
C −127
D +129
Explanation: Since MSB is 1, it is negative. Take 2’s complement to find magnitude: invert to 01111110, add 1 → 01111111 (=127). So value is −127.
If an 8-bit signed result exceeds +127, it causes
A Overflow
B Underflow
C Borrow only
D Parity error
Explanation: Signed overflow occurs when the true answer cannot fit the fixed range. For 8-bit 2’s complement, any result greater than +127 or less than −128 is out of range.
In 2’s complement, adding numbers of opposite signs can overflow
A Always
B Only for 0
C Never
D Only for 1
Explanation: Overflow in 2’s complement happens when adding two numbers of the same sign produces a result with opposite sign. Opposite-sign addition moves toward zero and cannot exceed range.
The binary 11111111 is −1 in
A Unsigned only
B Pure magnitude
C BCD format
D 2’s complement
Explanation: In 8-bit 2’s complement, all ones represents −1. This happens because taking 2’s complement of 00000001 gives 11111111.
In sign-magnitude representation, two zeros exist because
A Carry repeats
B Base changes
C Sign bit varies
D Hex digits differ
Explanation: Sign-magnitude uses MSB as sign and remaining bits as magnitude. Zero magnitude can have sign 0 (+0) or sign 1 (−0), creating two representations of zero.
In 1’s complement, −5 is formed by
A Flip bits only
B Flip then add 1
C Add 1 only
D Shift right
Explanation: In 1’s complement, negative is bitwise inversion of the positive pattern. +5 is 00000101, so −5 becomes 11111010. No “add 1” step is used.
In 1’s complement subtraction, the end-around carry is
A Discarded
B Made zero
C Added back
D Treated as sign
Explanation: 1’s complement subtraction adds the complement and then adds any carry-out back into the least significant bit. This end-around carry step is essential for correct results.
If 1’s complement addition produces all ones, it indicates
A +0
B −0
C Overflow
D Underflow
Explanation: In 1’s complement, all zeros is +0 and all ones is −0. Getting all ones as a final result corresponds to the negative zero representation.
Convert decimal 200 to binary
A 11001000
B 11101000
C 11011000
D 10101000
Explanation: 200 = 128 + 64 + 8. So bits for 128,64,32,16,8,4,2,1 become 1,1,0,0,1,0,0,0 giving 11001000₂.
Hex C8 equals which decimal
A 180
B 190
C 200
D 210
Explanation: C8₁₆ = 12×16 + 8 = 192 + 8 = 200. Hex is convenient because each digit maps directly to 4 binary bits.
Binary 11001000 equals which hex
A C8
B D8
C B8
D A8
Explanation: Group into nibbles: 1100 1000. 1100 is C and 1000 is 8. So 11001000₂ equals C8₁₆.
A quick binary-to-hex conversion uses grouping into
A 2 bits
B 3 bits
C 4 bits
D 5 bits
Explanation: One hex digit represents exactly 4 bits. So you group binary from right into sets of four and convert each group to its hex equivalent.
Binary 100110011001 equals hex
A 9C9
B 939
C 99C
D 999
Explanation: Group into nibbles: 1001 1001 1001. Each 1001₂ equals 9, so the hex number is 999₁₆.
Octal 777 equals decimal
A 500
B 512
C 511
D 513
Explanation: 777₈ = 7×64 + 7×8 + 7×1 = 448 + 56 + 7 = 511. It is also 9 bits all ones in binary.
A 3-bit Gray code sequence ensures consecutive codes differ by
A 1 bit
B 0 bits
C 2 bits
D 3 bits
Explanation: Gray code changes only one bit between consecutive values. This reduces misreading errors during transitions in encoders and digital sensors.
In a K-map, cells at opposite edges are considered
A Not adjacent
B Adjacent
C Diagonal only
D Invalid
Explanation: K-maps wrap around at edges because of Gray code ordering. This allows grouping across borders, leading to larger groups and more simplified Boolean expressions.
A 4-variable K-map can form a group of 8 cells only if they are
A Any 8 cells
B Diagonal only
C Rectangular adjacent
D Randomly chosen
Explanation: K-map groups must be rectangular blocks of 1,2,4,8, etc. adjacent cells. Adjacency includes wrap-around edges but not diagonals.
A K-map group of 4 cells eliminates how many variables
A 2 variables
B 1 variable
C 3 variables
D 4 variables
Explanation: In an n-variable map, grouping 2^k cells eliminates k variables. A group of 4 cells is 2², so it removes 2 variables, leaving fewer literals in the term.
A K-map group of 2 cells eliminates
A 2 variables
B 3 variables
C 4 variables
D 1 variable
Explanation: A pair group is 2¹ cells, so it eliminates 1 changing variable. The remaining variables stay constant across both cells and form the simplified product term.
In Boolean algebra, A ⊕ B equals 1 when
A A=B
B A=0 only
C A≠B
D B=0 only
Explanation: XOR outputs 1 only when inputs are different. This makes it useful for sum bits in adders and for detecting bit differences.
XOR of a bit with itself equals
A 0
B 1
C Same bit
D Complement bit
Explanation: A ⊕ A is always 0 because inputs are identical, so XOR condition “different” is never met. This property is used in error detection and algebraic simplifications.
XOR with 0 gives
A 0
B 1
C Same input
D Complement input
Explanation: A ⊕ 0 = A. Since 0 does not change the “difference” state, the output remains the original input. This is similar to identity behavior for XOR.
XNOR with 0 gives
A A
B A’
C 0
D 1
Explanation: XNOR is 1 when inputs are equal. So A XNOR 0 is 1 when A=0 and 0 when A=1, which is exactly NOT(A).
A NAND gate output becomes 1 for inputs
A 11 only
B 00 only
C Any not 11
D 01 only
Explanation: NAND is NOT(AND). Only AND(1,1)=1, so NAND(1,1)=0. For all other input pairs, AND is 0 and NAND becomes 1.
A NOR gate output becomes 1 for inputs
A 11 only
B Any not 00
C 01 only
D 00 only
Explanation: NOR is NOT(OR). OR(0,0)=0 so NOR outputs 1. Any input with 1 makes OR output 1, so NOR becomes 0.
A full adder carry-out can be written as
A AB + AC + BC
B A⊕B⊕C
C A+B+C
D (AB)’
Explanation: Carry-out is 1 when at least two of the three inputs are 1. The expression AB + AC + BC captures all cases where two or more inputs are 1.
Full adder sum is 1 when number of 1s is
A Even
B Always 3
C Odd
D Always 2
Explanation: Sum output equals A ⊕ B ⊕ Cin. XOR of three bits is 1 when an odd count of inputs is 1 (1 or 3), matching binary addition.
A multiplexer is often used to implement Boolean function by using
A Select as variables
B Random wiring
C Power as input
D Ground as output
Explanation: A MUX can realize Boolean functions by using select lines as variables and choosing input constants or variables appropriately. This is a common method for efficient logic implementation.
In a 4-to-1 MUX, number of data inputs is
A 2
B 8
C 4
D 16
Explanation: A 4-to-1 multiplexer has four data inputs and one output. Two select lines choose which one input is passed to the output at any time.
In a 4-to-1 MUX, select lines are
A 1
B 2
C 3
D 4
Explanation: Select lines needed are log₂(4)=2. Two select bits provide four combinations, allowing selection of one of the four input lines.
A 3-to-8 decoder has input bits
A 2
B 8
C 3
D 16
Explanation: A 3-to-8 decoder has 3 input bits and 8 outputs. Each input combination activates one output line, useful for address decoding in memory systems.
A 3-to-8 decoder outputs are
A 3
B 6
C 16
D 8
Explanation: With 3 input bits, there are 2³ = 8 possible combinations. Therefore, a standard decoder provides 8 output lines, one for each combination.
A priority encoder outputs the code for
A Highest active input
B Lowest active input
C Middle active input
D Random active input
Explanation: Priority encoders resolve multiple active inputs by selecting the highest-priority one (often highest-numbered). This prevents ambiguous outputs and is used in interrupt systems.
In SR latch, the invalid input condition is
A S=0, R=0
B S=0, R=1
C S=1, R=1
D S=1, R=0
Explanation: For a basic SR latch (NOR-based), S=R=1 forces both outputs low, breaking the complement rule and causing an invalid or indeterminate state when inputs return to normal.
JK flip-flop when J=K=1 causes
A Reset always
B Set always
C Hold output
D Toggle output
Explanation: JK flip-flop solves SR invalid case. When J=K=1, output toggles on each clock edge. This behavior is useful in counters and frequency division circuits.
In D flip-flop, next output equals
A Previous Q
B NOT D
C D input
D Clock only
Explanation: A D flip-flop stores the value on its D input at the active clock edge. After the edge, Q becomes D and holds that value until the next clock event.
ASCII code for uppercase letters and digits are examples of
A Printable characters
B Control codes only
C Parity bits
D BCD digits
Explanation: Printable ASCII includes letters, digits, punctuation, and symbols that can be displayed. Control codes like newline are non-printable and used for device or formatting control.
BCD addition sometimes needs correction by adding
A 1
B 3
C 8
D 6
Explanation: In BCD, if a 4-bit digit sum exceeds 9 or produces a carry, you add 6 (0110) to correct it back into valid BCD range. This ensures each digit stays 0–9.
A parity bit can fail to detect errors when
A One bit flips
B Two bits flip
C No bit flips
D MSB is 1
Explanation: Parity detects odd numbers of bit errors. If two bits flip, total parity may remain unchanged, so the parity check can miss that error.
Gray code is preferred in rotary encoders because
A Uses decimal digits
B Needs fewer wires
C One bit changes
D Has carry bit
Explanation: In position sensors, changing multiple bits at once can cause wrong readings due to timing differences. Gray code changes only one bit between adjacent positions, reducing transition errors.
A logic expression is in SOP form when it is
A OR of products
B AND of sums
C XOR of bits
D NOT of OR
Explanation: SOP means Sum of Products: multiple AND terms (products) are ORed together. It matches building circuits using AND gates feeding an OR gate, often derived from minterms.
A logic expression is in POS form when it is
A OR of products
B XOR of sums
C AND of sums
D NOT of AND
Explanation: POS means Product of Sums: multiple OR terms (sums) are ANDed together. It matches using OR gates feeding an AND gate, often derived from maxterms.
Converting SOP to NAND-only uses
A Decimal conversion
B ASCII mapping
C Parity grouping
D Bubble pushing
Explanation: Using De Morgan’s laws, inversions (bubbles) are moved across gate boundaries to convert AND/OR networks into NAND-only forms. This is a standard gate-level transformation method.
Converting POS to NOR-only mainly uses
A Division by 2
B Hex grouping
C De Morgan laws
D Parity check
Explanation: De Morgan’s laws allow OR and AND structures to be rewritten with complemented inputs/outputs, enabling implementation using only NOR gates for a NOR-only design.
In two’s complement, detecting overflow can use
A Carry into MSB XOR carry out
B LSB carry only
C Parity bit only
D Borrow bit only
Explanation: For 2’s complement addition, overflow occurs when carry into the sign bit differs from carry out of the sign bit. XOR of those carries gives a reliable overflow flag.
A combinational circuit’s output changes
A Only at clock edge
B With input changes
C Once per second
D Only after reset
Explanation: Combinational logic has no memory, so output responds immediately (after gate delays) to current input changes. Only sequential circuits rely on clocks and stored state.