Chapter 5: Number System and Digital Logic (Set-4)
When converting a large decimal to binary, the standard method repeatedly uses
A Multiply by 2
B Divide by 2
C Add by 2
D Divide by 10
Decimal-to-binary conversion commonly uses repeated division by 2. Each remainder (0 or 1) becomes a binary bit. Reading remainders from last to first gives the correct binary form.
In repeated division conversion, the binary bits are read in
A Reverse order
B Same order
C Random order
D Middle outward
Remainders are produced from least significant bit to most significant bit. So to form the final binary number, you read remainders from the last remainder back to the first remainder.
Convert decimal 29 to binary
A 11011
B 10111
C 11101
D 11110
29 = 16 + 8 + 4 + 1. Set those bit positions to 1 and others to 0: 11101₂. This matches binary place weights 16,8,4,2,1.
Convert binary 11010 to decimal
A 24
B 26
C 28
D 30
11010₂ equals 16 + 8 + 0 + 2 + 0 = 26. Add weights where bits are 1 to get the decimal value.
Convert decimal 73 to hexadecimal
A 4A
B 4B
C 5A
D 49
73 ÷ 16 = 4 remainder 9? Wait: 4×16=64, remainder 9, so it is 49₁₆ (not 4A). Correct hex for 73 is 49₁₆.
Convert hexadecimal 2F to decimal
A 31
B 63
C 47
D 79
2F₁₆ = 2×16 + 15 = 32 + 15 = 47. In hex, F represents 15, making conversions straightforward using place value 16.
Convert binary 111011 to octal
A 71
B 73
C 75
D 77
Group bits in threes: 111 011. 111₂ is 7 and 011₂ is 3, so the octal number is 73₈.
Convert octal 36 to binary
A 111010
B 011011
C 111100
D 011110
Each octal digit becomes 3 bits: 3→011 and 6→110. Combine to get 011110₂. Leading zeros do not change the value but keep grouping clear.
Convert binary 10101111 to hexadecimal
A BF
B A7
C AF
D 5F
Group into nibbles: 1010 1111. 1010₂ is A and 1111₂ is F, so the hex value is AF₁₆.
Convert hexadecimal 9C to binary
A 10011100
B 10011010
C 10101100
D 11110000
9 is 1001 and C is 1100 in binary. Combine: 1001 1100 → 10011100₂. Hex-to-binary conversion is direct by 4-bit mapping.
In unsigned binary addition, overflow is shown by
A MSB becomes 1
B Carry out MSB
C XOR becomes 0
D Borrow occurs
Unsigned overflow happens when the true sum needs an extra bit. The carry out of the most significant bit indicates the result exceeded the maximum representable value.
For 5-bit unsigned, maximum value equals
A 15
B 32
C 31
D 63
Maximum unsigned n-bit value is 2ⁿ−1. For 5 bits, 2⁵−1 = 32−1 = 31, represented as 11111₂.
For 5-bit 2’s complement, range is
A −15 to +16
B 0 to 31
C −31 to +31
D −16 to +15
In n-bit 2’s complement, range is −2^(n−1) to +2^(n−1)−1. For 5 bits, that becomes −16 to +15.
In 2’s complement, the pattern 10000000 (8-bit) means
A −127
B −128
C +128
D +0
In 8-bit 2’s complement, 10000000₂ represents the most negative value, −128. It has no positive counterpart within 8 bits, due to asymmetric range.
Which method is easiest for subtraction in digital hardware
A 1’s complement only
B Decimal subtraction
C 2’s complement add
D Repeated division
Hardware often uses the same adder circuit for both addition and subtraction. Subtraction A−B becomes A + (2’s complement of B), making design simpler and faster.
In 2’s complement, sign extension replicates
A LSB always
B MSB always
C Middle bit
D Parity bit
Sign extension keeps the numeric value same when increasing bit width. It copies the sign bit (MSB) into new higher bits, preserving negative or positive meaning.
In 1’s complement representation, −0 is
A 1111…1111
B 0000…0000
C 1000…0000
D 0111…1111
In 1’s complement, positive zero is all zeros, while negative zero is all ones. This dual-zero issue complicates arithmetic and comparisons compared to 2’s complement.
Which is true about 2’s complement zero
A Two different zeros
B Zero is 1111
C One zero only
D Zero is 1000
2’s complement has a single zero representation: all bits 0. This avoids the positive/negative zero problem and simplifies equality checks in digital systems.
A gate that outputs complement of OR is
A NAND
B NOR
C XOR
D XNOR
NOR equals NOT(OR). It outputs 1 only when all inputs are 0. NOR is a universal gate and can implement any Boolean function using only NOR gates.
A gate that outputs complement of AND is
A NOR
B XOR
C NOT
D NAND
NAND equals NOT(AND). It outputs 0 only when all inputs are 1. NAND is widely used in digital design because it is universal and easy to implement.
Which gate can act as inverter by tying inputs together
A AND
B OR
C NAND
D XOR
If both inputs of a NAND gate are connected to the same signal A, output becomes NOT(A). This allows building NOT using only NAND gates.
For XOR, output is 1 when
A Inputs equal
B Inputs differ
C All inputs 1
D All inputs 0
XOR outputs 1 for 01 and 10 in a 2-input case. It is useful for addition sum bits and parity because it detects differences between inputs.
For XNOR, output is 1 when
A Inputs equal
B Inputs differ
C Output forced 0
D Carry exists
XNOR is the complement of XOR. It outputs 1 for matching inputs (00 or 11), making it suitable for equality checking in comparators.
A truth table for n inputs contains
A n rows
B n² rows
C 2ⁿ rows
D 2n rows
Each input can be 0 or 1. With n inputs, there are 2×2×…×2 (n times) = 2ⁿ combinations, so a complete truth table needs 2ⁿ rows.
Boolean identity: A + 0 equals
A 0
B A
C 1
D A’
OR with 0 leaves the variable unchanged. This is the identity law for OR, widely used to remove unnecessary terms from Boolean expressions.
Boolean identity: A · 1 equals
A 0
B 1
C A’
D A
AND with 1 leaves the variable unchanged. This is the identity law for AND and helps simplify expressions when a term is multiplied by 1.
Boolean null law: A + 1 equals
A 0
B A
C 1
D A’
OR with 1 always gives 1 because if any input is true, the OR result is true. This rule helps reduce expressions quickly.
Boolean null law: A · 0 equals
A 1
B 0
C A
D A’
AND with 0 always gives 0 because one false condition forces the entire AND to false. This is used in masking and simplifying circuits.
Idempotent rule for AND is
A A+A=A’
B A·A’=1
C A+0=0
D A·A=A
Idempotent laws state repeating a variable doesn’t change it: A·A = A and A + A = A. It removes duplicate literals in simplified logic.
Complement rule: A + A’ equals
A 0
B A
C 1
D A’
A OR NOT(A) is always true. Whatever A is, one of them will be 1, so the OR result is always 1. This is central to simplification.
Complement rule: A · A’ equals
A 1
B 0
C A
D A’
A AND NOT(A) can never be 1 simultaneously. One must be 0, so their AND is always 0. It represents a contradiction in logic.
Absorption: A + AB simplifies to
A A
B AB
C B
D A+B
A + A·B = A. If A is 1, output is already 1. If A is 0, both terms become 0. So AB does not add new cases.
Absorption: A(A + B) simplifies to
A B
B A+B
C AB
D A
A·(A+B) = A. When A is 0, output is 0; when A is 1, output is 1. The term (A+B) becomes irrelevant once multiplied by A.
Canonical SOP uses
A Only maxterms
B Only complements
C Only minterms
D Only constants
Canonical Sum of Products is written as an OR of minterms, where each minterm includes all variables once (either complemented or not), matching input combinations where output is 1.
Canonical POS uses
A Only minterms
B Only maxterms
C Only XOR terms
D Only NAND terms
Canonical Product of Sums is written as an AND of maxterms. Each maxterm includes all variables once and corresponds to an input combination where output is 0.
A K-map for 4 variables has cells
A 8
B 12
C 32
D 16
A K-map has 2ⁿ cells for n variables. For 4 variables, 2⁴ = 16 cells. Each cell corresponds to one minterm (one input combination).
A K-map grouping rule requires group size
A Any size
B Prime number
C Power of two
D Always four
Groups must be 1, 2, 4, 8, etc. This ensures variables cancel properly, leading to correct simplification. Non-power-of-two groups do not eliminate variables consistently.
Gray code ordering in K-map helps because
A More cells exist
B Adjacent differ 1 bit
C Decimal becomes easier
D Carry reduces
K-map adjacency follows Gray code, meaning neighboring cells differ by only one variable. This makes grouping valid because grouped cells share common terms except one variable that can be eliminated.
A half adder cannot add
A Carry-in bit
B Two data bits
C Sum output
D Carry output
Half adder adds only two 1-bit inputs. It produces Sum and Carry but lacks a carry-in input. For adding with carry from previous stage, a full adder is required.
A full adder can be built using
A One NOT gate
B One OR gate
C Two half adders
D One AND gate
A full adder can be made from two half adders and an OR gate. First half adder adds A and B, second adds Sum with Cin, and OR combines carry outputs.
A multiplexer output equals
A All inputs together
B Always 0
C Always 1
D Selected input only
A multiplexer forwards exactly one chosen input to the output based on select lines. It is used for data routing, resource sharing, and implementing Boolean functions.
A demultiplexer routes input to
A Many outputs
B One chosen output
C All outputs
D No output
A demultiplexer takes one input and sends it to exactly one output line chosen by select lines. It acts like a controlled switch for distributing signals.
A decoder usually produces output in
A Binary form only
B Floating analog
C One-hot form
D Random pattern
In a one-hot output, only one line is active for a given input code. This is useful for selecting one device or memory row among many based on binary input.
A latch differs from flip-flop mainly by
A Level sensitivity
B Uses no gate
C Always synchronous
D Always combinational
Latches are level-sensitive; they can change output while enable is active. Flip-flops are typically edge-triggered, updating only on a clock edge, giving better timing control in sequential circuits.
A JK flip-flop avoids the problem of
A XOR ambiguity
B SR invalid state
C Parity mismatch
D Hex conversion
In SR flip-flop, S=R=1 is invalid. JK flip-flop modifies this case to toggle the output instead of becoming invalid, making it more reliable for counters.
A toggle (T) flip-flop changes state when T is
A 0
B X only
C 1
D Z only
When T=1 and a clock edge occurs, a T flip-flop toggles its output (0→1 or 1→0). When T=0, it holds the previous state.
In basic ASCII, a character code uses
A 5 bits
B 6 bits
C 9 bits
D 7 bits
Standard ASCII is 7-bit, giving 128 possible codes. It includes control characters, digits, uppercase/lowercase letters, and punctuation, enabling consistent text encoding across systems.
BCD is mainly useful when
A Doing binary-only math
B Showing decimal digits
C Making XOR gates
D Increasing CPU speed
BCD represents each decimal digit separately in 4 bits. It is useful for calculators and digital displays where correct decimal digit representation is needed without binary-to-decimal conversion errors.
Even parity bit is chosen so total 1s become
A Odd count
B Prime count
C Even count
D Zero count
With even parity, the parity bit is set to make the total number of 1s in the transmitted word even. Receiver checks this to detect many single-bit errors.
A logic circuit without memory is classified as
A Combinational logic
B Sequential logic
C Register logic
D Storage logic
Combinational circuits have outputs determined only by current inputs. They contain no storage elements like flip-flops, so they do not depend on past states, unlike sequential logic.